1. Field of the Invention
The present invention relates to the field of error compensating loops and more specifically to stabilized integrated phase locked loop systems.
2. Related Application
The present application is related to copending application Ser. No. 92,478, filed Sept. 3, 1987, entitled "Stabilized Phase Locked Loop".
3. Prior Art
Phase locked loop systems are well known in the prior art wherein these loops are utilized to maintain stable frequency, phase and other circuit parameters. Phase locked loops must have stable and controlled operating characteristics, immune to voltage, temperature and circuit fabrication variations. This is especially so during the operation of the phase locked loop when environmental conditions can change readily. Primary parameters which are essential for the operation of a stable phase locked loop are loop gain and filter characteristics.
Typically, dynamic loop characteristics of integrated phase locked loops require off-chip adjustment to control the loop parameters. This is achieved by adjusting the loop filter, or changing the loop gain and are typically made with respect to an external standard reference. Further, there are two specifications imposed on most phase locked loop systems which by nature are diametrically opposite to each other. These two specifications are settling time and jitter response.
For a phase locked loop to have a satisfactory settling time the loop should respond fast to external data changes but the response must not be too fast in order to have a good jitter specification. A trade off must be made between these two specifications and often it is difficult to satisfy both requirements simultaneously. In prior art, a common solution is to create a two or multiple gain loop system in which a two gain loop is utilized. A fast mode is used to satisfy the required settling time specification and after the loop has achieved lock, the high gain mode is switched off. When the high gain mode is off, the jitter specifications are satisfied because of the low gain.
It is appreciated then that what is required is a phase locked loop system which is capable of being independent of various circuit process and environmental conditions without the use of external compensation and which also is capable of having a satisfactory settling time with a good immunity to read data jitter.